1. Field of the Invention
The present invention relates to integrated circuits (IC), more particularly to insertion of scan hardware using electronic design automation (EDA) tools.
2. Description of the Related Art
With regularity over the past years, integrated circuits (IC) such as microcontrollers have gotten smaller, yet in the meanwhile have become more powerful. Today, it is not uncommon for a microcontroller to contain millions of transistors. Naturally, the job of designing these electronic circuits has also grown correspondingly more difficult. What was once accomplished by a single designer or a small group of designers, the job of designing microcontrollers must now be typically performed by a large team of designers or multiple teams of designers.
Specialized microcontrollers with integrated communication features are becoming particularly attractive for communication applications. A microcontroller, or an embedded controller, is uniquely suited to combining functionality onto one monolithic semiconductor substrate (i.e., chip). By embedding various communication features within a single chip, a communications microcontroller may support a wide range of communication applications.
Furthermore, designers used manual design techniques, i.e., components laid out by hand on blueprints, to design ICs. With today""s complex design and competitive pressures to provide new generation of products having improved function and performance, companies typically use design automation (DA) technology utilizing computer-aided design (CAD) or computer-aided engineering (CAE). One type of DA known as electronic design automation (EDA) involved the designer""s use of computer programs for the design and test of ICs. The EDA computer programs are often called applications or tools.
Using the EDA tool, a design engineer can break a large circuit into smaller functional units and specify constraints and requirements such as desired inputs and outputs of the functional units. The EDA tool then suggests solutions, often drawing on a vast digital library of possible circuits. In this manner, large circuits are decomposed into more manageable units that can be designed individually, perhaps by groups of design engineers working more or less independently. The result is that the overall design process is significantly faster than it would be otherwise.
For example, United Design Automation, Inc. of Austin, Tex. publishes Silicon Arena, a software package that provides, among other things, a graphical synthesis environment in which a design engineer can constrain and synthesize a design using a set of templates for creating logic synthesis command scripts. Information relative to a specific design may be stored in template files and compiled into a design run as needed. Silicon Arena provides a mechanism for maintaining and sharing synthesis scripts and parameters. Silicon Arena enables a user to create a gate-level netlist (a short hand description of a schematic indicating connections among larger elements) including Design for Test (DFT) scan chains. In particular, the Silicon Arena synthesis page allows a user to configure synthesis constraints, compiled high-level Register Transfer Level (RTL) code which takes into account the constraints, generate data for other teams of design engineers who place and route the design in light of constraints, and generates schematics used for final circuit layout configuration. Silicon Arena thus gives the users the ability to easily constrain and synthesis a design using a known set of synthesis templates.
Therefore, as a result of circuits becoming increasing complex, DFT tools have become increasingly important by insuring the ability to test the circuit. Automated test tools such as FastScan and FlexTest both published by Mentor Graphics of Wilsonville, Oreg., have been developed to provide this functionality. During the design process, selected sequential elements such as flip-flops and latches are replaced with their scan equivalent elements. In addition, sets and resets are modified so that they are not asserted during testing, and three-state buses are modified to reduce conflicts. Also, an Automatic Test Pattern Generator (ATPG) may generate a set of xe2x80x9cscan vectorsxe2x80x9d to provide a high volt coverage of a circuit. More sophisticated testing procedures that employs scan cells, such as latches or flip-flops, together forming a scan chain, built into the circuit can perform testing at a functional unit level.
Thus, the importance of EDA tools is evident. However, current EDA tools suffer from many shortcomings. First, the EDA tools generally cannot automatically insert scan cells into circuits that utilize multiple clocks. Timing conflicts result in the scan chain when scan cells operate at different frequencies. In addition, due to the size and complexity of scan chain, current EDA tools do not take into account the drivers needed for the complex scan chain. Furthermore, EDA tools generally cannot be used to automatically insert scanned cells into ICs that include legacy cores. When an IC is in the scan mode, the outputs of the legacy cores are not taken into account, resulting in erroneous test data.
Current EDA tools suffer from many short comings that affect design and manufacture of integrated circuits, such as microcontrollers. According to one embodiment of the present invention, a script in a high-level language, such as VHDL (VHSIC Hardware Description for Language) or Verilog(copyright) or Synopsys Synthesis Script (Synopsys, Inc. of Mountain View, Calif.), for circuit incorporating elements utilizing multiple clocks is written to incorporate multiplexers in a scan chain. The script is compiled or synthesized into a netlist. Multiplexing in a single clock into scan cells allows scan data to be clocked out while the microcontroller is in a scan mode.
Next, according to an embodiment of the present invention, a script in a high-level language, such as VHDL or Verilog(copyright) or Synopsys Synthesis Script, for a circuit incorporating many scan cells, is written to incorporate drivers for a SCAN_EN signal cells. For complex scan chains, additional drivers generally need to be incorporated into the circuit to drive the scan chain.
Next, a script in a high-level language, such as VHDL or Verilog(copyright) or Synopsys Synthesis Script, for a circuit incorporating many scan cells is written to incorporate a fake clock. The fake clock is used to force the EDA tool to have different scan chains for each clock domain. This results in fewer scan chains crossing clock boundaries. Once the scan chains are inserted, the fake clocks are removed and synthesis continues.
Last, according to one aspect of the present invention, a script in a high-level language, such as VHDL or Verilog(copyright) or Synopsys Synthesis Script, for a circuit incorporating legacy cores is written to isolate legacy cores from scan testing. Signals from the legacy core generally have little controllability since it comes from a legacy core without scan or other recent test ability techniques. These output signals are isolated from affecting the other blocks under test to provide full control and observability to these signals.